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ks57c5532/p5532 product overview 1 - 1 1 product overview overview the ks57c5532/p5532 single-chip cmos microcontroller has been designed for high-performance using samsung's newest 4 -bit cpu core, sam47 (samsung arrangeable microcontrollers). the KS57P5532 is a microcontroller which has 32-kbyte one-time-programmable eprom but its functions are same to ks57c5532. with its dtmf generator, 8-bit serial i/o interface, and ver satile 8-bit timer/counters, the ks 57c5532/p5532 offers an excel lent design solution for a wide variety of telecommunication applica tions. up to 55 pins of the 64-pin sdip or qfp package can be dedicated to i/o. seven vectored interrupts provide fast re sponse to internal and external events. in addition, the ks 57c5532/p5532 's advanced cmos technol ogy provides for low power consumption and a wide op erating voltage range. development support the samsung microcontroller development system, smds, provides you with a complete pc-based develop- ment environment for ks57-series microcontrollers that is powerful, reliable, and portable. in addition to its window-based program development structure, the smds toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. the samsung generalized assembler (sama) has been designed specifically for the smds environment and accepts assembly language sources in a variety of microprocessor formats. sama generates industry-standard hex files that also contain program control data for smds compatibility.
product overview ks57c5532/p5532 1 - 2 features summary memory 1 k 4-bit ram 32 k 8-bit rom 55 i/o pins input only: 4 pins i/o: 43 pins n-channel open-drain i/o (s/w) : 8 pins memory-mapped i/o structure data memory bank 15 dtmf generator 16 dual-tone frequencies for tone dialing 8-bit basic timer programmable internal timer watchdog timer two 8-bit timer/counters programmable interval timer external event counter function timer/counters clock outputs to tclo0 and tclo1 pins external clock signal divider serial i/o interface clock generator watch timer time interval generation: 0.5 s, 3.9 ms at 32.768 khz 4 frequency outputs to the buz pin 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode lsb-first or msb-first transmission selectable bit sequential carrier supports 8-bit serial data transfer in arbitrary format interrupts 3 external interrupt vectors 4 internal interrupt vectors 2 quasi-interrupts power-down modes idle: only cpu clock stops stop: main s ystem clock stops subsystem clock stop mode oscillation sources crystal, ceramic for main system clock crystal oscillator for subsystem clock main system clock frequency: 3.579545 mhz (typical) subsystem clock frequency: 32.768 khz (typical) cpu clock divider circuit (by 4, 8, or 64) instruction execution times 0.67, 1.33, 10.7 s at 6.0 mhz 1.12, 2.23, 17.88 s at 3.579545 mhz 122 s at 32.768 khz operating temperature ? 40 c to 85 c operating voltage range 1.8 v to 5.5 v (at 3 mhz) 2.7 v to 5.5 v (at 6 mhz) package types 64 sdip, 64 qfp
ks57c5532/p5532 product overview 1 - 3 block diagram stack pointer arithmetic and logic unit instruction decoder internal interrupts interrupt control block clock 32 k byte program memory xt out x out xt in x in basic timer watch timer i/o port 12 serial i/o port i/o port 0 i/o port 13 program counter program status word flags watch-dog timer dtmf generator input port1 i/o port 2 i/o port 3 reset int0, int1, int2 int4 p0.0/ sck p0.1/so p0.2/si p0.3/btco p1.0/ int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/ tclo0 p2.1/tclo1 p2.2/clo p2.3/buz p4.0-p4.3 p5.0-p5.3 p3.0/ tclo0 p3.1/tclo1 p3.2 p3.3 i/o port 8 i/o port 9 1 k x 4-bit data memory p13.0-p13.2 p12.0-p12.3 i/o port 10 i/o port 11 p11.0-p11.3 p10.0-p10.3 p9.0-p9.3 p8.0-p8.3 i/o port 6 i/o port 7 p7.0-p7.3/ ks4-ks7 p6.0-p6.3/ ks0-ks3 8-bit timer/ counter 1 8-bit timer/ counter 0 i/o port 4 i/o port 5 dtmf figure 1 -1 . ks 57c5532/p5532 simplified block diagram
product overview ks57c5532/p5532 1 - 4 pin assignments p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p13.2 p13.1 p13.0 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p0.3/btco p0.2/si p0.1/so p0.0/ sck p 10.3 p10.2 p10.1 p10.0 p11.3 p11.2 p11.1 p11.0 p12.3 p12.2 p12.1 p12.0 p3.3 p3.2 test dtmf v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v ss p9.0 p9.1 p9.2 p9.3 p8.0 p8.1 p8.2 p8.3 p7.0/ks4 p7.1/ks5 p7.2/ks6 p7.3/ks7 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 xt out xt in x in x out reset p5.0 p5.1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 p3.0/tcl0 p3.1/tcl1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ks57c5532 (64-sdip-750) figure 1 -2 . ks 57c5532/p5532 pin assignment diagrams
ks57c5532/p5532 product overview 1 - 5 p8.0 p9.3 p9.2 p9.1 p9.0 v ss p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p13.2 p13.1 p13.0 32 31 30 29 28 27 26 25 24 23 22 21 20 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p0.3/btco p0.2/si p0.1/so p0.0/ sck p10.3 p10.2 p10.1 p10.0 p11.3 p11.2 p11.1 p11.0 p12.3 p12.2 p12.1 p5.3 p4.0 p4.1 p4.2 p4.3 p3.0/tcl0 p3.1/tcl1 v dd dtmf test p3.2 p3.3 p12.0 ks57c5532 (64-qfp-1420f) figure 1 -2 . ks 57c5532/p5532 pin assignment diagrams (continued)
product overview ks57c5532/p5532 1 - 6 pin descriptions table 1 - 1. ks 57c5532/p5532 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up re sistors are automatically disabled for output pins. 15 (8) 14 (7) 13 (6) 12 (5) so si btco p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test is possible. 4 -bit pull-up resistors are assignable by software to p ort 1 . 1 (61) 2 (60) 3 (59) 4 (58) int0 int1 int2 int4 p2.0 p2.1 p2.2 p2.3 i/o same as port 0. 11 (4) 10 (3) 9 (2) 8 (1) tclo0 tclo1 clo buz p3.0 p3.1 p3.2 p3.3 i/o same as port 0. 34 (27) 33 (26) 29 (22) 28 (21) tcl0 tcl1 sclk (1) sdat (1) p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable to input pins and are automatically disable for output pins. n-channel open-drain or push-pull output can be selected by software. port 4 and 5 can be paired to support 8-bit data transfer. 38?35 (31?28) 42?39 (35?32) ? p6.0?p6.3 p7.0?p7.3 i/o 4-bit i/o ports. 1-bit or 4-bit read/write and test is possible. port 6 pins are individually software configurable as input or output. 4-bit pull -up resistors are software assignable; pull-up re sistors are automati cally disabled for output pins. ports 6 and 7 can be paired to enable 8-bit data transfer. 51?48 (44?41) 55?52 (48?45) ks0?ks3 ks4?ks7 p8.0?p8.3 i/o same as port 0. 59?56 (52?49) ? p9.0?p9.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable ; pull-up re sistors are automatically disabled for output pins. 63?60 (56?53) ? notes 1. sclk and sdat are used for KS57P5532 only. 2. parentheses indicate pin number for 64 qfp package.
ks57c5532/p5532 product overview 1 - 7 table 1 - 1. ks 57c5532/p5532 pin descriptions (continued) pin name pin type description number share pin p10.0?p10.3 p11.0?p11.3 i/o same as port 9. ports 10 and 11 can be paired to support 8-bit data transfer. 19?16 (12?9) 23?20 (16?13) ? p12.0?p12.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-down resistors are software assignable; pull-down re sistors are automatically disabled for output pins. 27?24 (20?17) ? p13.0?p13.2 i/o 3-bit i/o port; characteristics are same as port 9. 7?5 (64?62) ? dtmf o dtmf output. 31 (24) ? i/o serial i/o interface clock signal 15 (8) p0.0 so i/o serial data output 14 (7) p0.1 si i/o serial data input 13 (6) p0.2 btco i/o basic timer clock output 12 (5) p0.3 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. int0 is synchronized to system clock. 4, 3 (61, 60) p1.0, p1.1 int2 i quasi-interrupt with detection of rising edges 2 (59) p1.2 int4 i external interrupt with detection of rising and falling edges. 1 (58) p1.3 tclo0 i/o timer/counter 0 clock output 11 (4) p2.0 tclo1 i/o timer/counter 1 clock output 10 (3) p2.1 clo i/o clock output 9 (2) p2.2 buz i/o 2 khz, 4 khz, 8 khz, or 16 khz frequency output at the watch timer clock frequency of 32.768 khz for buzzer sound 8 (1) p2.3 tcl0 i/o external clock input for timer/counter 0 34 (27) p3.0 tcl1 i/o external clock input for timer/counter 1 33 (26) p3.1 ks0?ks3 ks4?ks7 i/o quasi-interrupt inputs with falling edge detection 51?48 (44?41) 55?52 (48?45) p6.0?p6.3 p7.0?p7.3 note : parentheses indicate pin number for 64 qfp package.
product overview ks57c5532/p5532 1 - 8 table 1 - 1. ks 57c5532/p5532 pin descriptions (concluded) pin name pin type description number share pin v dd ? power supply 32 (25) ? v ss ? ground 64 (57) ? i reset signal 43 (36) ? x in, x out ? crystal, ceramic, or r/c oscillator signal for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out ) 45, 44 (38, 37) ? xt in, xt out ? crystal oscillator signal for subsystem clock. (for external clock input, use xt in and input xt in 's reverse phase to xt out ) 46, 47 (39, 40) ? test ? chip test input pin. hold gnd when the device is operating. 30 (23) ? note : parentheses indicate pin number for 64 qfp package.
ks57c5532/p5532 product overview 1 - 9 table 1 - 2. overview of ks 57c5532/p5532 pin data pin names share pins i/o type reset value circuit type p0.0?p0.3 , so, si, btco i/o input d-4 p1.0?p1. 3 int0, int1, int2 , int4 i input a-1 p2.0?p2.3 tclo0, tclo1, clo, buz i/o input d-2 p3.0?p3.1 tcl0, tcl1 i/o input d-4 p3.2?p3.3 ? i/o input d-2 p4.0?p4.3 p5.0?p5.3 ? i/o input e-2 p6.0?p6.3 p7.0?p7.3 ks0?ks3 ks4?ks7 i/o input d-4 p8.0?p8.3 ? i/o input d-2 p9.0?p9.3 ? i/o input d-2 p10.0?p10.3 p11.0?p11.3 ? i/o input d-2 p12.0?p12.3 ? i/o input d-6 p13.0?p13.2 ? i/o input d-2 dtmf ? o high impedence g-6 x in , x out xt in , xt out ? ? ? ? ? i ? b nc ? ? ? ? v dd , v ss ? ? ? ?
product overview ks57c5532/p5532 1 - 10 pin circuit diagrams p-channel n-channel in v dd figure 1-3. pin circuit type a schmitt trigger pull-up resistor v dd pull-up resistor enable in p-channel figure 1-4. pin circuit type a-1 schmitt trigger in v dd pull-up resistor figure 1-5. pin circuit type b p-channel n-channel v dd out output disable data figure 1-6. pin circuit type c
ks57c5532/p5532 product overview 1 - 11 p-channel i/o output disable data circuit type c pull-up enable v dd figure 1-7. pin circuit type d-2 p-channel i/o output disable data circuit type c pull-up enable v dd schmitt trigger figure 1-8. pin circuit type d-4 i/o output disable data circuit type c pull-down enable figure 1-9. pin circuit type d-6 v dd pne output disable data pull-up enable v dd i/o figure 1-10. pin circuit type e-2
product overview ks57c5532/p5532 1 - 12 dtmf out disable - +
ks 57c5532/p5532 electrical data 14- 1 14 electrical data overview in this section, information on ks57c5532 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? ab solute maximum ratings ? d.c. electrical characteristics ? system clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in and x out ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data ks 57c5532/p5532 14- 2 table 14- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 15 ma all i/o ports active ? 30 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) all i/o ports, total + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note : the values for output current low ( i ol ) are calculated as peak value duty . table 14- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ?v ih4 0.7 v dd ? v dd v v ih2 ports 0, 1, 3, 6, 7, and reset 0.8 v dd v dd v ih3 ports 4 and 5 with pull-up resistors assigned 0.7 v dd v dd v ih4 x in, x out and xt in v dd ? 0.1 v dd input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 3, 6, 7, and reset 0.2 v dd v il3 x in, x out and xt in 0.1
ks 57c5532/p5532 electrical data 14- 3 table 14- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh i oh = ? 1 ma ports except 1 v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4,5 only ? ? 2 v v dd = 1.8 to 5.5 v, i ol = 1.6ma ? 0.4 v v ol2 v dd = 4.5 v to 5.5 v i ol = 4ma all out ports except ports 4,5 2 v v dd = 1.8 to 5.5 v, i ol = 1.6ma 0.4 v input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v i = v dd x in, x out and xt in 20 input low leakage current i lil1 v i = 0 v all input pins except below and reset ? ? - 3 m a i lil2 v i = 0 v x in, x out and xt in - 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? - 3 pull-up resistor r l1 v dd = 5 v; v i = 0 v except reset 25 45 100 k w v dd = 3 v 50 89 200 r l3 v dd = 5 v; v i = 0 v; reset 100 212 400 v dd = 3 v 200 441 800 pull-down resistor r l4 v dd = 5 v; v i = v dd ; port 12 25 46 100 v dd = 3 v 50 95 200
electrical data ks 57c5532/p5532 14- 4 table 14- 2. d.c. electrical characteristics (con cluded ) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (dtmf on) run mode; v dd = 5.0 v 10% 3.58 mhz crystal oscillator; c1 = c2 = 22 pf ? 3.0 5.0 ma v dd = 3 v 10% 1.6 3.0 i dd2 run mode; v dd = 5.0 v 10% 6.0 mhz 2.7 8.0 (dtmf off) crystal oscillator; c1 = c2 = 22 pf 3.58 mhz 2.0 4.0 v dd = 3 v 10% 6.0 mhz 1.3 4.0 3.58 mhz 0.9 2.3 i dd3 idle mode; v dd = 5 v 10% 6.0 mhz 0.8 2.5 3.58 mhz 0.7 1.8 v dd = 3 v 10% 6.0 mhz 0.3 1.5 3.58 mhz 0.2 1.0 i dd4 run mode; v dd = 3.0 v 10% 32 khz crystal oscillator ? 12 .5 30 m a i dd5 idle mode; v dd = 3.0 v 10% 32 khz crystal oscillator 4.5 15 i dd 6 stop mode; v dd = 5 v 10% scmod = 0000b ? 1.9 5 stop mode; v dd = 3 v 10% xt = 0v 0.6 3 stop mode; v dd = 5 v 10% scmod = 0100b 0.2 3 stop mode; v dd = 3 v 10% 0.1 2 row tone level (2) v row v dd = 2.0 v to 5.5 v r l =12 k w ; temp = ? 30 to 60 c ? 16 ? 14 ? 11 dbv ratio of column to row tone (2) db cr v dd = 2.0 v to 5.5 v r l = 12 k w ; temp = ? 30 to 60 c 1 2 3 db distortion (2) (dual tone) thd v dd = 2.0 v to 5.5 v 1 mhz band, r l = 12 k w temp = ? 30 to 60 c ? ? 5 % notes : 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up resistors. 2. dtmf electrical characteristics. 3. for d.c. electrical values , the power control register (pcon) must be set to 0011b.
ks 57c5532/p5532 electrical data 14- 5 table 14- 3. main system clock oscillator characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3 v ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3 v ? ? 10 ms external clock x in x out x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 x in input high and low level width (t xh, t xl ) ? 83.3 ? 1250 ns notes : 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval requir ed for oscillator stabilization after a power-on occurs, or when stop mode is terminated.
electrical data ks 57c5532/p5532 14- 6 table 14-4 . recommended oscillator constants (t a = ? 40 c to + 85 c) manufacturer series number (1) frequency range load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz?6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscilla tor frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in.
ks 57c5532/p5532 electrical data 14- 7 table 14-5 . subsystem clock oscillator characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt i n c1 c2 xt out oscillation frequency (1) ? 32 32.76 8 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 5.5 v ? ? 10 s external clock xt i n xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xh, t xl ) ? 5 ? 15 s notes : 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabil ization after a power-on occurs or when stop mode is terminated. table 14-6 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf
electrical data ks 57c5532/p5532 14- 8 table 14-7 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time (1) t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 s v dd = 1.8 v to 5 .5 v 1.33 tcl0, tcl1 input frequency f ti0, f ti1 v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5 .5 v 1 m hz tcl0, tcl1 input high, low width t tih0, t til0 t tih1, t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 1.8 v to 5 .5 v 1.8 cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 670 v dd = 1.8 v to 5 .5 v external sck source 3200 internal sck source 3800 sck high, low width t kh, t kl v dd = 2.7 v to 5.5 v external sck source 335 ? ? ns internal sck source t kcy ? 2 50 v dd = 1.8 v to 5 .5 v external sck source 1600 internal sck source t kcy ? 2 150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 1.8 v to 5.5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 1.8 v to 5.5 v external sck source 600 internal sck source 500
ks 57c5532/p5532 electrical data 14- 9 table 14-7 . a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output delay for sck to so t kso (note) v dd = 2.7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 1.8 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth, t intl int0 , int1, int2, int4, ks0?ks7 10 ? ? s reset input low width t rsl input 10 ? ? s note : r (1 k w ) and c (100 pf) are the load resistance and load capacitance of the so output line . 1.5 mhz cpu clock 1.05 mhz 0.75 mhz 15.625 khz main oscillator frequency (divided by 4) 4.2 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 2.7 1.8 figure 14- 1. standard operating voltage range
electrical data ks 57c5532/p5532 14- 10 table 14-8 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.5 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by ? 2 17 /fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start- u p. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
ks 57c5532/p5532 electrical data 14- 11 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 14- 2. stop mode release timing when initiated b y execution of stop instrction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating (interrupt request) figure 14- 3. stop mode release timing when initiated b y interrupt request
electrical data ks 57c5532/p5532 14- 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14- 4. a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 14- 5. clock timing measurement at x in (xt in ) tcl t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 14-6 . tcl 0/1 timing
ks 57c5532/p5532 electrical data 14- 13 reset t rsl 0.2 v dd figure 14-7 . input timing for signal int0, 1, 2, 4, ks0 to ks7 t inth t intl 0.8 v dd 0.2 v dd figure 14-8 . input timing for external interrupts and quasi-interrupts
electrical data ks 57c5532/p5532 14- 14 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t ks o t si k t ksi 0.8 v dd 0.2 v dd si so figure 14-9 . serial data transfer timing
ks57c5532/p5532 mechanical data 15- 1 15 mechanical data this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram 64-qfp-1420f #64 #1 note : dimensions are in millimeters. 20.00 0.2 14.00 0.2 17.90 0.3 23.90 0.3 (1.00) (1.00) 0.80 0.20 0.05-0.25 2.65 0.10 3.00 max 0.15 +0.10 -0.05 0-8 1.00 0.15 max 0.40+0.10 -0.05 0.80 0.20 0.10 max figure 15- 1. 64-qfp-1420 f package dimensions
mechanical data ks57c5532/p5532 15- 2 64-sdip-750 17.00 0 .2 #64 #33 #32 #1 19.05 note : dimensions are in millimeters. 58.20 max 57.80 0 .2 0.51 min 3.30 0.3 4.10 0.2 5.08 max (1.34) 1.778 0.45 0.1 1.00 0.1 0.25 + 0.1 - 0.05 0-15 figure 15- 2 . 64- sdip - 75 0c package dimensions
ks57c5532/p5532 ks5 7p5532 otp 16- 1 1 6 KS57P5532otp overview the KS57P5532 single-chip cmos microcontroller is the otp (one time programmable) version of the ks57c5532 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the KS57P5532 is fully compatible with the ks57c5532, both in function and in pin configuration. because of its simple programming requirements, the KS57P5532 is ideal for use as an evaluation chip for the ks57c5532.
KS57P5532 otp ks57c5532/p5532 16- 2 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p13.2 p13.1 p13.0 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p0.3/btco p0.2/si p0.1/so p0.0/ sck p 10.3 p10.2 p10.1 p10.0 p11.3 p11.2 p11.1 p11.0 p12.3 p12.2 p12.1 p12.0 sdat /p3.3 sclk /p3.2 v pp / test dtmf v dd/ v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v ss / v ss p9.0 p9.1 p9.2 p9.3 p8.0 p8.1 p8.2 p8.3 p7.0/ks4 p7.1/ks5 p7.2/ks6 p7.3/ks7 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 xt out xt in x in x out reset/ reset p5.0 p5.1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 p3.0/tcl0 p3.1/tcl1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 note: the bold indicate a otp pin name. KS57P5532 (64-sdip-750) figure 16-1. KS57P5532 pin assignments (64-sdip)
ks57c5532/p5532 ks5 7p5532 otp 16- 3 p8.0 p9.3 p9.2 p9.1 p9.0 v ss/ v ss p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p13.2 p13.1 p13.0 32 31 30 29 28 27 26 25 24 23 22 21 20 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p8.1 p8.2 p8.3 p7.0/ks4 p7.1/ks5 p7.2/ks6 p7.3/ks7 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 xt out xt in x in x out reset/ reset p5.0 p5.1 p5.2 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p0.3/btco p0.2/si p0.1/so p0.0/ sck p10.3 p10.2 p10.1 p10.0 p11.3 p11.2 p11.1 p11.0 p12.3 p12.2 p12.1 p5.3 p4.0 p4.1 p4.2 p4.3 p3.0/tcl0 p3.1/tcl1 v dd / v dd dtmf test/ v pp p3.2/ sclk p3.3/ sdat p12.0 KS57P5532 (64-qfp-1420f) note: the bold indicate a otp pin name. figure 16-2. KS57P5532 pin assignments (64-qfp)
KS57P5532 otp ks57c5532/p5532 16- 4 table 16-1. descriptions of pins used to read/write the eprom pin name during programming pin no. i/o function sdat 28 (21) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. sclk 29 (22) i serial clock pin. input only pin. v pp (test) 30 (23) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) hold gnd when otp is operating. reset 43 (36) i chip initialization v dd /v ss 32 (25) / 64 (57) i logic power supply pin. v dd should be tied to + 5 v during programming. note: parentheses indicate pin number for 64 qfp package. table 16-2. comparison of KS57P5532 and ks57c5532 features characteristic KS57P5532 ks57c5532 program memory 32 k byte eprom 32 k byte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5v pin configuration 64 sdip/qfp 64 sdip/qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the KS57P5532, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15?a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5v 0 0000h 0 eprom program 12.5v 0 0000h 1 eprom verify 12.5v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
ks57c5532/p5532 ks5 7p5532 otp 16- 5 table 16-4 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 15 ma all i/o ports active ? 30 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) all i/o ports, total + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note : the values for output current low ( i ol ) are calculated as peak value duty . table 16-5 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ? v ih4 0.7 v dd ? v dd v v ih2 ports 0, 1, 3, 6, 7, and reset 0.8 v dd v dd v ih3 ports 4 and 5 with pull-up resistors assigned 0.7 v dd v dd v ih4 x in, x out and xt in v dd ? 0.1 v dd input low voltage v il1 all input pins except those specified below for v il2 ? v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 3, 6, 7, and reset 0.2 v dd v il3 x in, x out and xt in 0.1
KS57P5532 otp ks57c5532/p5532 16- 6 table 16-5 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh i oh = ? 1 ma ports except 1 v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4,5 only ? ? 2 v v dd = 2.0 to 5.5 v, i ol = 1.6ma ? 0.4 v v ol2 v dd = 4.5 v to 5.5 v i ol = 4ma all out ports except ports 4,5 2 v v dd = 2.0 to 5.5 v, i ol = 1.6ma 0.4 v input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v i = v dd x in , x out and xt in 20 input low leakage current i lil1 v i = 0 v all input pins except below and reset ? ? - 3 m a i lil2 v i = 0 v x in , x out and x t in ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 pull-up resistor r l1 v dd = 5 v; v i = 0 v except reset 25 45 100 k w v dd = 3 v 50 89 200 r l3 v dd = 5 v; v i = 0 v; reset 100 212 400 v dd = 3 v 200 441 800 pull-down r l4 v dd = 5 v ; v i = v dd ; port 12 25 46 100 resistor v dd = 3 v 50 95 200
ks57c5532/p5532 ks5 7p5532 otp 16- 7 table 16-5 . d.c. electrical characteristics (con cluded ) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (dtmf on) run mode; v dd = 5.0 v 10% 3.58 mhz crystal oscillator; c1 = c2 = 22 pf ? 3.0 5.0 ma v dd = 3 v 10% 1.6 3.0 i dd2 run mode; v dd = 5.0 v 10% 6.0 mhz 2.7 8.0 (dtmf off) crystal oscillator; c1 = c2 = 22 pf 3.58 mhz 2.0 4.0 v dd = 3 v 10% 6.0 mhz 1.3 4.0 3.58 mhz 0.9 2.3 i dd3 idle mode; v dd = 5 v 10% 6.0 mhz 0.8 2.5 3.58 mhz 0.7 1.8 v dd = 3 v 10% 6.0 mhz 0.3 1.5 3.58 mhz 0.2 1.0 i dd4 run mode; v dd = 3.0 v 10% 32 khz crystal oscillator ? 12 .5 30 m a i dd5 idle mode; v dd = 3.0 v 10% 32 khz crystal oscillator 4.5 15 i dd 6 stop mode; v dd = 5 v 10% scmod = 0000b ? 1.9 5 stop mode; v dd = 3 v 10% xt = 0 v 0.6 3 stop mode; v dd = 5 v 10% scmod = 0.2 3 stop mode; v dd = 3 v 10% 0100b 0.1 2 row tone level (2) v row v dd = 2.0 v to 5.5 v r l =12 k w ; temp = ? 30 to 60 c ? 16 ? 14 ? 11 dbv ratio of column to row tone (2) db cr v dd = 2.0 v to 5.5 v r l =12 k w ; temp = ? 30 to 60 c 1 2 3 db distortion (2) (dual tone) thd v dd = 2.0 v to 5.5 v 1 mhz band, r l = 12 k w temp = ? 30 to 60 c ? ? 5 % notes : 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up resistors. 2. dtmf electrical characteristics. 3. for d.c. electrical values , the power control register (pcon) must be set to 0011b.
KS57P5532 otp ks57c5532/p5532 16- 8 table 16-6 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3.0 stabilization time (2) v dd = 3 v ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3.0 stabilization time (2) v dd = 3 v ? ? 10 ms external clock x in x out x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3.0 x in input high and low level width (t xh, t xl ) ? 83.3 ? 1250 ns notes : 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization aft er a power-on occurs, or when stop mode is terminated.
ks57c5532/p5532 ks5 7p5532 otp 16- 9 table 16-7 . recommended oscillator constants (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) manufacturer series number (1) frequency range load cap ( pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz?6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. table 16-8 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt i n c1 c2 xt out oscillation frequency (1) ? 32 32.76 8 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 5.5 v ? ? 10 s external clock xt i n xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xh, t xl ) ? 5 ? 15 s notes : 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabil ization after a power-on occurs or when stop mode is terminated.
KS57P5532 otp ks57c5532/p5532 16- 10 table 16-9 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf 1.5 mhz cpu clock 1.05 mhz 0.75 mhz 15.625 khz main oscillator frequency (divided by 4) 4.2 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 2.7 1.8 figure 16-3 . standard operating voltage range

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